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Si3035
3 .3 V F C C / J AT E DIR E C T A C C E S S A R R A N G E M E N T
Features
Complete DAA includes the following:
! ! ! ! ! !
3.3 V to 5 V Digital/Analog Power Supplies JATE Filter Option 86 dB Dynamic Range TX/RX Paths Daisy-Chaining for Up to Eight Devices Integrated Ring Detector 3000 V Isolation
! ! ! ! ! ! ! ! !
Support for Caller ID Low Profile SOIC Packages Direct Interface to DSPs Integrated Modem Codec Compliant with FCC Part 68 Low-Power Standby Mode Proprietary ISOcapTM Technology Pin Compatible with Si3034, Si3032 Optional IIR Digital Filter
Ordering Information See page 50.
Pin Assignments
Applications
! !
Si3021 (SOIC)
! !
V.90 Modems Voice Mail Systems
Fax Machines Set Top Boxes
MCLK FSYNC SCLK VD SDO SDI FC/RGDT RESET
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
OFHK RGDT/FSD M0 VA GND C1A M1 AOUT
Description
The Si3035 is an integrated direct access arrangement (DAA) chipset that provides a digital, low-cost, solid-state interface to a telephone line. Available in two 16-pin small outline packages, it eliminates the need for an analog front end (AFE), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3035 dramatically reduces the number of discrete components and cost required to achieve compliance with FCC Part 68. The Si3035 interfaces directly to standard modem DSPs and supports all FCC and JATE out-of-band noise requirements. International support is provided by the pin compatible Si3034.
Si3021 (TSSOP)
SDO SDI FC/RGDT RESET AOUT M1 C1A GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VD SCLK FSYNC MCLK OFHK RGDT/FSD M0 VA
Functional Block Diagram
Si3021
Si3012
Si3012 (SOIC or TSSOP)
MCLK SCLK FSYNC SDI SDO FC/RG T Isolation Interface Isolation Interface DC Termination VREG 2 VREG DCT REXT IG ND RNG 1 RNG 2 O ff-Hook QB QE Digital Interface Hybrid O ut In TX RX HYBD
TSTA TSTB IGND C1B RNG1 RNG2 QB QE
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
TX NC RX REXT DCT HYBD VREG2 VREG
RG DT/FSD O FHK MO DE RESET AO UT Control Interface
Ring Detect
US Patent # 5,870,046 US Patent # 6,061,009 Other Patents Pending
Si3035-DS12
Rev. 1.2 12/00
Copyright (c) 2000 by Silicon Laboratories
S i3 03 5
2
Rev. 1.2
Si3035 TA B L E O F CON T E N T S
Section Page
4 15 16 17 18 18 18 18 19 19 19 20 24 24 25 25 25 26 26 32 32 32 33 34 45 46 48 50 51 52 54
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ring Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Improved JATE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Hook Line Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Current Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . In-Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix--UL1950 3rd Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si3021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si3012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOIC Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 1.2
3
S i3 03 5
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter1 Ambient Temperature Si3021 Supply Voltage, Analog Si3021 Supply Voltage, Digital3
Notes:
Symbol TA VA VD
Test Condition K-Grade
Min2 0 4.75 3.0
Typ 25 5.0 3.3/5.0
Max2 70 5.25 5.25
Unit C V V
1. The Si3035 specifications are guaranteed when the typical application circuit (including component tolerances) and any Si3021 and any Si3012 are used. See Figure 16 on page 15 for typical application circuit.
2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise stated. 3. The digital supply, VD, can operate from either 3.3 V or 5.0 V. The Si3021 supports interface to 3.3 V logic when operating from 3.3 V. The 3.3 V operation applies to both the serial port and the digital signals RGDT, OFHK, RESET, M0, and M1.
Table 2. Loop Characteristics
(VA = Charge Pump, VD = +3.3 V 0.3 V, TA = 0 to 70C for K-Grade, Refer to Figure 1)
Parameter DC Termination Voltage DC Termination Voltage DC Ring Current (with caller ID) DC Ring Current (w/o caller ID) AC Termination Impedance Operating Loop Current Loop Current Sense Bits Ring Voltage Detect Ring Frequency On-Hook Leakage Current Ringer Equivalence Num. (with caller ID) Ringer Equivalence Num. (w/o caller ID)
Symbol VTR VTR IRDC IRDC ZACT ILP LCS VRD FR ILK REN REN
Test Condition IL = 20 mA IL = 105 mA
Min -- 12 -- -- -- 20
Typ -- -- -- -- 600 -- 155 18 -- -- 1.0 0.2
Max 7.7 -- 1 20 -- 120 -- 26 68 1 1.67 --
Unit V V mA A mA mA VRMS Hz A -- --
LCS = Fh
180 13 15
VBAT = -48 V
-- -- --
TIP + 600 Si3012 VTR 10 F - IL
RING
Figure 1. Test Circuit for Loop Characteristics
4 Rev. 1.2
Si3035
Table 3. DC Characteristics, VD = +5 V
(VA = +5 V 5%, VD = +5 V 5%, TA = 0 to 70C for K-Grade)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Power Supply Current, Analog Power Supply Current, Digital1 Total Supply Current, Sleep Mode
1
Symbol VIH VIL VOH VOL IL IA ID IA + ID IA + ID
Test Condition
Min 3.5 --
Typ -- -- -- -- -- 0.3 14 1.3 0.04
Max -- 0.8 -- 0.4 10 1 18 2.5 0.5
Unit V V V V A mA mA mA mA
IO = -2 mA IO = 2 mA
3.5 -- -10
VA pin VD pin PDN = 1, PDL = 0 PDN = 1, PDL = 1
-- -- -- --
Total Supply Current, Deep Sleep1,2
Notes: 1. All inputs at 0.4 or VD - 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded (Static IOUT = 0 mA). 2. RGDT is not functional in this state.
Table 4. DC Characteristics, VD = +3.3 V
(VA = Charge Pump, VD = +3.3 V 0.3 V, TA = 0 to 70C for K-Grade)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Power Supply Current, Analog1,2 Power Supply Current, Digital
3 3
Symbol VIH VIL VOH VOL IL IA ID IA + ID IA + ID VA
Test Condition
Min 2.0 --
Typ -- -- -- -- -- 0.3 9 1.2 0.04 4.6
Max -- 0.8 -- 0.35 10 1 12 2.5 0.5 5.00
Unit V V V V A mA mA mA
IO = -2 mA IO = 2 mA
2.4 -- -10
VA pin VD pin PDN = 1, PDL = 0 PDN = 1, PDL = 1 Charge Pump On
-- -- -- -- 4.3
Total Supply Current, Sleep Mode
Total Supply Current, Deep Sleep3,4 Power Supply Voltage, Analog1,5
V
Notes: 1. Only a decoupling capacitor should be connected to VA when the charge pump is on. 2. There is no IA current consumption when the internal charge pump is enabled and only a decoupling cap is connected to the VA pin. 3. All inputs at 0.4 or VD - 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded (Static IOUT = 0 mA). 4. RGDT is not functional in this state. 5. The charge pump is recommended to be used only when VD < 4.5 V. When the charge pump is not used, VA should be applied to the device before VD is applied on power up if driven from separate supplies.
Rev. 1.2
5
S i3 03 5
Table 5. AC Characteristics
(VA = Charge Pump, VD = +3.3 V 0.3 V, TA = 0 to 70C for K-Grade)
Parameter Sample Rate1 PLL1 Output Clock Frequency Transmit Frequency Response Receive Frequency Response Transmit Full Scale Level2 (0 dB gain) Receive Full Scale Level Dynamic Range4 Dynamic Range5 Total Harmonic Distortion6 Dynamic Range (call progress AOUT) THD (call progress AOUT) AOUT Full Scale Level AOUT Output Impedance Mute Level (call progress AOUT) Dynamic Range (caller ID mode) Caller ID Full Scale Level (0 dB gain)2
2,3
Symbol Fs FPLL1
Test Condition Fs = FPLL2/5120 FPLL1 = FMCLK M1/N1
"
Min 7.2 36 -- -- -- --
Typ -- -- 16 16 0.98 0.98 86 84 -84 -- 1.0 0.75 VD 10 -- 60 0.8
Max 11.025 58 -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit kHz MHz Hz Hz VPEAK VPEAK dB dB dB dB % VPP k dB dB VPEAK
Low -3 dB corner Low -3 dB corner VTX VRX DR DR THD DRAO THDAO VIN = 1 kHz, -3 dBFS VIN = 1 kHz, -3 dBFS VIN = 1 kHz, -3 dBFS VIN = 1 kHz VIN = 1 kHz
(0 dB gain)
80 -- -- 60 -- -- -- -90
DRCID VCID
VIN = 1 kHz, -13 dBFS
-- --
Notes: 1. See Figure 23 on page 22. 2. Parameter measured at TIP and RING of Figure 16 on page 15. 3. Receive Full Scale Level will produce - 0.9 dBFS at SDO. 4. DR = 3 dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement bandwidth is 300 to 3400 Hz. Sample Rate = 9.6 kHz, Loop Current = 40 mA. 5. DR = 3 dB + 20 log (RMS signal/RMS noise). Applies to both the transmit and receive paths. Measurement bandwidth is 15 to 3400 Hz. Sample Rate = 9.6 kHz, Loop Current = 40 mA. 6. THD = 20 log (RMS distortion/RMS signal). Applies to both the transmit and receive paths. Sample Rate = 9.6 kHz, Loop Current = 40 mA.
6
Rev. 1.2
Si3035
Table 6. Absolute Maximum Ratings
Parameter DC Supply Voltage Input Current, Si3021 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Symbol VD, VA IIN VIND TA TSTG Value -0.5 to 6.0 10 -0.3 to (VD + 0.3) -40 to 100 -65 to 150 Unit V mA V C C
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 7. Switching Characteristics--General Inputs
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70C for K-Grade, CL = 20 pF)
Parameter1 Cycle Time, MCLK MCLK Duty Cycle Rise Time, MCLK Fall Time, MCLK MCLK Before RESET RESET Pulse Width
2 3
Symbol tmc tdty tr tf tmr trl tmxr
Min 16.67 40 -- -- 10 250 150
Typ -- 50 -- -- -- -- --
Max 1000 60 5 5 -- -- --
Unit ns % ns ns cycles ns ns
M0, M1 Before RESET
Notes: 1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD - 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform. 2. The minimum RESET pulse width is the greater of 250 ns or 10 MCLK cycle times. 3. M0 and M1 are typically connected to VD or GND and should not be changed during normal operation.
tr MCLK tm r trl M0, M1 tm xr
tm c
tf
V IH V IL
RESET
Figure 2. General Inputs Timing Diagram
Rev. 1.2
7
S i3 03 5
Table 8. Switching Characteristics--Serial Interface (DCE = 0)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70C for K-Grade, CL = 20 pF)
Parameter Cycle time, SCLK SCLK duty cycle Delay time, SCLK to FSYNC Delay time, SCLK to SDO valid Delay time, SCLK to FSYNC Setup time, SDI before SCLK Hold time, SDI after SCLK Setup time, FC before SCLK Hold time, FC after SCLK
Symbol tc tdty td1 td2 td3 tsu th tsfc thfc
Min 354 -- -- -- -- 25 20 40 40
Typ 1/256 Fs 50 -- -- -- -- -- -- --
Max -- -- 10 20 10 -- -- -- --
Unit ns % ns ns ns ns ns ns ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD - 0.4 V, VIL = 0.4 V
tc
SCLK
VOH VOL t d3
t d1
FSYNC (m ode 0)
t d3
FSYNC (m ode 1)
t d2
16 Bit SDO
D15
t su
D14
th
D1
D0
16 Bit SDI
D15
D14
D1 tsfc
D0 thfc
FC
Figure 3. Serial Interface Timing Diagram
8
Rev. 1.2
Si3035
Table 9. Switching Characteristics--Serial Interface (DCE = 1, FSD = 0)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70C for K-Grade, CL = 20 pF)
Parameter1,2 Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK to FSYNC Delay Time, SCLK to FSYNC Delay Time, SCLK to SDO valid Delay Time, SCLK to SDO Hi-Z Delay Time, SCLK to RGDT Delay Time, SCLK to RGDT Setup Time, SDO Before SCLK Hold Time, SDO After SCLK Setup Time, SDI Before SCLK Hold Time, SDI After SCLK
Symbol tc tdty td1 td2 td3 td4 td5 td6 tsu th tsu2 th2
Min 354 -- -- -- 0.25tc - 20 -- -- -- 25 20 25 20
Typ 1/256 Fs 50 -- -- -- -- -- -- -- -- -- --
Max -- -- 10 10 0.25tc + 20 20 20 20 -- -- -- --
Unit ns % ns ns ns ns ns ns ns ns ns ns
Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD - 0.4 V, VIL = 0.4 V. 2. Refer to the section "Multiple Device Support" on page 25 for functional details.
32 S C LK s
tc
16 S C LK s
16 S C LK s
SCLK t d1 FSYNC (m ode 1) t d2 t d2
td5 FSYNC (m ode 0) td3 SDO (m aster) t su D15 D14 th D13 D0
td6
t d5
t d4
t d3 SDO (slave 1) D15 t d5 FSD (M ode 0) FSD (M ode 1) t su2 SDI D15
D 14
td2
t h2 D13 D0
Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)
Rev. 1.2
9
S i3 03 5
Table 10. Switching Characteristics--Serial Interface (DCE = 1, FSD = 1)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70C for K-Grade, CL = 20 pF)
Parameter1,2 Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK to FSYNC Delay Time, SCLK to FSYNC Delay Time, SCLK to SDO valid Delay Time, SCLK to SDO Hi-Z Delay Time, SCLK to RGDT Setup Time, SDO Before SCLK Hold Time, SDO After SCLK Setup Time, SDI Before SCLK Hold Time, SDI After SCLK
Symbol tc tdty td1 td2 td3 td4 td5 tsu th tsu2 th2
Min 354 -- -- -- 0.25tc - 20 -- -- 25 20 25 20
Typ 1/256 Fs 50 -- -- -- -- -- -- -- -- --
Max -- -- 10 10 0.25tc + 20 20 20 -- -- -- --
Unit ns % ns ns ns ns ns ns ns ns ns
Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD - 0.4 V, VIL = 0.4 V. 2. Refer to the section "Multiple Device Support" on page 25 for functional details.
tc SCLK td1 FSYNC (m ode 1) td3 SDO (m aster) D15 tsu D14 th D13 D0 td3 SDO (slave 1) FSD tsu2 SDI D15
D14
td2
td4
D15 td5
th2 D1 D0
Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1)
10
Rev. 1.2
Si3035
Table 11. Digital FIR Filter Characteristics--Transmit and Receive
(VA = Charge Pump, VD = +5 V 5%, Sample Rate = 8 kHz, TA = 0 to 70C for K-Grade)
Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay
Symbol F(0.1 dB) F(3 dB)
Min 0 0 -0.1 -- -74
Typ -- -- -- 4.4 -- 12/Fs
Max 3.3 3.6 0.1 -- -- --
Unit kHz kHz dB kHz dB sec
tgd
--
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 6, 7, 8, and 9.
Table 12. Digital IIR Filter Characteristics--Transmit and Receive
(VA = Charge Pump, VD = +5 V 5%, Sample Rate = 8 kHz, TA = 0 to 70C for K-Grade)
Parameter Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay
Symbol F(3 dB)
Min 0 -0.2 -- -40
Typ -- -- 4.4 -- 1.6/Fs
Max 3.6 0.2 -- -- --
Unit kHz dB kHz dB sec
tgd
--
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 10, 11, 12, and 13. Figures 14 and 15 show group delay versus input frequency.
Rev. 1.2
11
S i3 03 5
Attenuation--dB
Attenuation--dB
Input Frequency--Hz
Input Frequency--Hz
Figure 6. FIR Receive Filter Response
Figure 8. FIR Transmit Filter Response
Attenuation--dB
Input Frequency--Hz
Attenuation--dB
Input Frequency--Hz
Figure 7. FIR Receive Filter Passband Ripple
Figure 9. FIR Transmit Filter Passband Ripple
For Figures 6-9, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample rate as follows:
F(0.1 dB) = 0.4125 Fs F(- 3 dB) = 0.45 Fs
where Fs is the sample frequency.
12
Rev. 1.2
Si3035
Attenuation--dB
Input Frequency--Hz
Attenuation--dB
Input Frequency--Hz
Figure 10. IIR Receive Filter Response
Figure 12. IIR Transmit Filter Response
Attenuation--dB
Input Frequency--Hz
Attenuation--dB
Input Frequency--Hz
Figure 11. IIR Receive Filter Passband Ripple
Figure 13. IIR Transmit Filter Passband Ripple
For Figures 10-13, all filter plots apply to a sample rate of Fs = 8 kHz. The filters scale with the sample rate as follows:
F(-3 dB) = 0.45 Fs
where Fs is the sample frequency.
Rev. 1.2
13
S i3 03 5
Delay--s
Input Frequency--Hz
Delay--s
Input Frequency--Hz
Figure 14. IIR Receive Group Delay
Figure 15. IIR Transmit Group Delay
14
Rev. 1.2
Typical Application Circuit
Decoupling cap for U1 VD
VCC C10 R3 10 C3 Z4
Decoupling cap for U1 VA
No Ground Plane In DAA Section
D3 BAV99 R1
Q1 R5
M0 RGDTb OFHKb U1 MCLK FSYNCb SCLK SDO SDI FC RESETb 1 2 3 4 5 6 7 8 MCLK FSYNC SCLK VD SDO SDI FC RESET OFHK RGDT M0 VA GND C1A M1 AOUT 16 15 14 13 12 11 10 9 U2 Si3012 TSTA TX TSTB NC2 IGND RX C1B REXT RNG1 DCT RNG2 HYBD QB VREG2 QE VREG R4 R21 Q2
+
R27
R28
C1
Si3021 SOIC Pinout AOUT C30 D4 BAV99 C2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9 C12
C5
R18 R6
C23 R2
+ Z1 C20
M1
Z5
C6
C16
Q3
Rev. 1.2
C4
R23
C8
R10
FB2 RING
D2 C9
C25
C32
C11
RV1 RV2
D1 R22 C7 R9
C24
C31
FB1
TIP
Note 1: R3 is not required when Vcc=3.3 V and the charge pump is enabled (CPE = 1). Note 2: If JATE support is not required, R21, C12 and C23 may be removed (R21 is effectively 0 ohms) and R4 should be changed to a 604 ohm, 1/4 W, +- 1%. Note 3: See Appendix for applications requiring UL 1950 3rd Edition compliance.
Si3035
Figure 16. Typical Application Schematic
15
S i3 03 5
Bill of Materials
Table 13. Component Values--Typical Application
Component1
C1,C4 C2 C3 C5 C6,C10,C16 C7,C8,C9 C11 C12
2
Value
150 pF, 3 kV, X7R, 20% Not Installed 0.22 F, 16 V, X7R, 20% 1 F, 16 V, Tant/Elec, 20% 0.1 F, 16 V, X7R, 20% 15 nF, 250 V, X7R, 20% 39 nF, 16 V, X7R, 20% 2.7 nF, 16 V, X7R, 20% 0.1 F, 16 V, Tant/Elec/X7R, 20%
3
Supplier(s)
Novacap, Venkel, Johanson, Murata, Panasonic, SMEC
Novacap, Johanson, Murata, Panasonic, SMEC
C232 C24, C25, C31,C32 C30
4
1000 pF, 3 kV, X7R, 10% Not Installed Dual Diode, 300 V, 225 mA BAV99 Dual Diode, 70 V, 350 mW Ferrite Bead A42, NPN, 300 V A92, NPN, 300 V Sidactor, 275 V, 100 A MOV, 240 V 51 , 1/2 W 5% 15 , 1/4 W 5% Not Installed 301 , 1/10 W, 1% 36 k, 1/10 W 5% 2 k, 1/10 W 5% 20 k, 1/10 W 5% 10 , 1/10 W 5% Si3021 Si3012 Zener diode, 18 V Zener diode, 5.6 V, 1/2 W
Novacap, Venkel, Johanson, Murata, Panasonic, SMEC
D1,D25 D3,D4 FB1,FB2 Q1,Q3 Q2 RV1 RV2 R1 R2 R36 R42,R18,R212 R5,R6 R9,R10 R22,R23 R27,R28 U1 U2 Z1 Z4,Z5
Central Semiconductor Diodes, Inc., OnSemiconductor, Fairchild Murata OnSemiconductor, Fairchild OnSemiconductor, Fairchild Teccor, ST Microelectronics, Microsemi, TI Panasonic
Silicon Labs Silicon Labs Vishay, Rohm, OnSemiconductor Diodes, Inc., OnSemiconductor, Fairchild
Notes: 1. The following reference designators were intentionally omitted: C13-C15, C17-C22, C26-C29, R7, R8, R11-R17, R19, and R20. 2. If JATE support is not required, C12, and C23 may be removed. 3. Alternate population option is C24, C25 (2200 pF, 3 kV, X7R, 10% and C31, C32 not installed). 4. Install only if needed for improved radiated emissions performance (10 pF, 16 V, NPO, 10%). 5. Several diode bridge configurations are acceptable (suppliers include General Semi, Diodes Inc.) 6. If the charge pump is not enabled (with the CPE bit in Register 6), VA must be 4.75 to 5.25 V. R3 can be installed with a 10 , 1/10 W, 5% if VD is also 4.75 to 5.25 V.
16
Rev. 1.2
Si3035
Analog Output
Figure 17 illustrates an optional application circuit to support the analog output capability of the Si3035 for call progress monitoring purposes. The ARM bits in Register 6 allow the receive path to be attenuated by 0 dB, -6 dB, or -12 dB. The ATM bits, which are also in Register 6, allow the transmit path to be attenuated by -20 dB, -26 dB, or -32 dB. Both the transmit and receive paths can also be independently muted.
+5 V C2 AOUT C1 C6 R1 R3 3 6 5 C5 C3 R2 Speaker + C4
+ 2- 4
Figure 17. Optional Connection to AOUT for a Call Progress Speaker
`
Table 14. Component Values--Optional Connection to AOUT
Symbol C1 C2, C3, C5 C4 C6 R1 R2 R3 U1 Value 2200 pF, 16 V, 20% 0.1 F, 16 V, 20% 100 F, 16 V, Elec. 20% 820 pF, 16 V, 20% 3 k, 1/10 W, 5% 10 , 1/10 W, 5% 47 k, 1/10 W, 5% LM386
Rev. 1.2
17
S i3 03 5
Functional Description
The Si3035 is an integrated chipset that provides a low-cost, isolated, silicon-based interface to the telephone line. The Si3035 saves cost and board area by eliminating the need for a modem AFE or serial codec. It also eliminates the need for an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3035 solution requires only a few low-cost, discrete components to achieve full compliance with FCC Part 68 and JATE out-of-band noise requirements. See Figure 16 on page 15 for a typical application circuit. See the pin-compatible Si3034 or Si3044 data sheets for designs requiring global support. The Si3035 North America/Japan DAA offers a number of new features not supported by the Si3032 device. These include operation from a single 3.3 V power supply, JATE (Japan) filter option, finer resolution for both transmit and receive levels on AOUT (call progress output), daisy-chaining for up to eight devices, and an optional IIR filter. Table 15 summarizes the new Si3035 features. procedure:
1. Program the PLLs with registers 7 to 9 (N1[7:0], M1[7:0], N2[3:0] and M2[3:0]) to the appropriate divider ratios for the supplied MCLK frequency and desired sample rate, as defined in "Clock Generation Subsystem" on page 20. 2. Wait until the PLLs are locked. This time is between 100 S and 1 ms. 3. Write an 0x80 into Register 6. This enables the charge pump for the VA pin, powers up the line-side chip (Si3012), and enables the AOUT for call progress monitoring.
After this procedure is complete, the Si3035 is ready for ring detection and off-hook.
Isolation Barrier
The Si3035 achieves an isolation barrier through a low-cost, high-voltage capacitor in conjunction with Silicon Laboratories' proprietary ISOcap signal processing techniques. These techniques eliminate any signal degradation due to capacitor mismatches, common mode interference, or noise coupling. As shown in Figure 16 on page 15, the C1, C2, and C4 capacitors isolate the Si3021 (DSP-side) from the Si3012 (line-side). All transmit, receive, control, and caller ID data are communicated through this barrier. The ISOcap inter-chip communication is disabled by default. To enable it, the PDL bit in Register 6 must be cleared. No communication between the Si3021 and Si3012 can occur until this bit is cleared. The clock generator must be programmed to an acceptable sample rate prior to clearing the PDL bit.
Table 15. New Si3035 Features
Category Daisy-Chaining Optional IIR Filter Receive Gain Transmit Attenuation VA VD JATE Support AOUT Levels (dB) Si3032 -- -- 0, 6 dB 0, -3 dB 5V 3.3 V or 5 V -- 0, mute Si3035 Up to 8 Devices Yes 0, 3, 6, 9, 12 dB 0, -3, -6 -9, -12 dB 3.3 V* or 5 V 3.3 V or 5 V Yes 0, -6, -12, mute
Off-Hook
The communication system generates an off-hook command by applying logic 0 to the OFHK pin or writing a logic 1 to bit 0 of control Register 5. The OFHK pin must be enabled by setting bit 1 (OHE) of Register 5. With OFHK at logic 0, the system is in an off-hook state. This state is used to seize the line for incoming/outgoing calls and can also be used for pulse dialing. With OFHK at logic 1, negligible DC current flows through the hookswitch. When a logic 0 is applied to the OFHK pin, the hookswitch transistor pair, Q1 and Q2, turn on. The net effect of the off-hook signal is the application of a termination impedance across TIP and RING and the flow of DC loop current. The termination impedance has both an AC and a DC component. The AC termination impedance is a 604- resistor, which is connected to the TX pin. The DC termination is a 51- resistor, which is connected to the DCT pin. When executing an off-hook sequence, the Si3035 requires 1548/Fs seconds to complete the off-hook and provide phone line data on the serial link. This includes the 12/Fs filter group delay. If necessary, for the shortest
*Note: The VA supply is internally generated by an on-chip charge pump.
Initialization
When the Si3035 is initially powered up, the RESET pin should be asserted. When the RESET pin is deasserted, the registers will have default values. This reset condition guarantees the line-side chip (Si3012) is powered down with no possibility of loading the line (i.e., off-hook). The following is an example initialization
18
Rev. 1.2
Si3035
delay, a higher Fs may be established prior to executing the off-hook, such as an Fs of 10.286 kHz. The delay allows line transients to settle prior to normal use.
Improved JATE Support
The HYBD pin connects to a node on the internal hybrid cancellation circuit providing a pin for a balancing capacitor, C12. C23 adds the necessary transmit out-of-band filtering required to meet JATE out-of-band noise specifications. The addition of C23 alters the transmit path frequency response which must be balanced with capacitor C12 to obtain maximum hybrid cancellation. Products using the Si3035 which have been submitted for JATE approval should document a waiver for the JATE DC Termination specification. This specification is met in the Si3034 global DAA device.
Ring Detect
The ring signal enters the Si3035 through low value capacitors connected to TIP and RING. RGDT is a clipped, half-wave rectified version of the ringing waveform. See Figure 18 for a timing diagram of the RGDT pin. The integrated ring detect of the Si3035 allows the device to present the ring signal to the DSP, through the serial port, with no additional signaling required. The signal sent to the DSP is a clipped version of the original ring signal. In addition, the Si3035 passes through the caller ID data unaltered. The system can also detect an occurring ring by the status of the RDT bit of Register 5. This bit is a read-only bit that is set when the line-side device detects a ring signal at RNG1 and RNG2. The RDT bit clears when the system either goes off-hook or 4.5 to 9 seconds after the last ring is detected. If caller ID is supported in the system, the designer can enable the Si3035 to pass this information to the SDO output. Following the completion of the first ring, the system should set the ONHM bit (Register 5, bit 3). This bit must be cleared at the conclusion of the receipt of the caller ID data and prior to the next ring burst. The Si3021 can support a wake-up-on-ring function using the RGDT signal. Refer to "Power Management" on page 24 for more details .
Digital Interface
The Si3035 has two serial interface modes that support most standard modem DSPs. The M0 and M1 mode pins select the interface mode. The key difference between these two serial modes is the operation of the FSYNC signal. Table 16 summarizes the serial mode definitions.
Table 16. Serial Modes
Mode 0 1 2 3 M1 M0 Description
0 0 FSYNC frames data 0 1 FSYNC pulse starts data frame 1 0 Slave mode 1 1 Reserved
First Ring 0.2-3.0 seconds RNG1/ RNG2
0.5-1.5 Sec.
> 0.2 Sec.
DATA
RGDT
SDO
DIGITIZED LINE SIGNAL
Figure 18. Ring Detect Timing
Rev. 1.2
19
S i3 03 5
The digital interface consists of a single, synchronous serial link which communicates both telephony and control data. In Serial mode 0 or 1, the Si3021 operates as a master, where the master clock (MCLK) is an input, the serial data clock (SCLK) is an output, and the frame sync signal (FSYNC) is an output. The MCLK frequency and the value of the sample rate control registers 7, 8, 9, and 10 determine the sample rate (Fs). The serial port clock, SCLK, runs at 256 bits per frame, where the frame rate is equivalent to the sample rate. Refer to "Clock Generation Subsystem" on page 20 for more details on programming sample rates. The Si3035 transfers 16-bit or 15-bit telephony data in the primary timeslot and 16-bit control data in the secondary timeslot. Figure 19 and Figure 20 show the relative timing of the serial frames. Primary frames occur at the frame rate and are always present. To minimize overhead in the external DSP, secondary frames are present only when requested. Two methods exist for transferring control information in the secondary frame. The default power-up mode uses the LSB of the 16-bit transmit (TX) data word as a flag to request a secondary transfer. In this mode, only 15-bit TX data is transferred, resulting in a loss of SNR but allowing software control of the secondary frames. As an alternative method, the FC pin can serve as a hardware flag for requesting a secondary frame. The external DSP can turn on the 16-bit TX mode by setting the SB bit of Register 1. In the 16-bit TX mode, the hardware FC pin must be used to request secondary transfers.
Com m unications Fram e 1 (CF1)
Figure 21 and Figure 22 illustrate the secondary frame read cycle and write cycle, respectively. During a read cycle, the R/W bit is high and the 5-bit address field contains the address of the register to be read. The contents of the 8-bit control register are placed on the SDO signal. During a write cycle, the R/W bit is low and the 5-bit address field contains the address of the register to be written. The 8-bit data to be written immediately follows the address on SDI. Only one register can be read or written during each secondary frame. See "Control Registers" on page 34 for the register addresses and functions. In serial mode 2, the Si3021 operates as a slave device, where the MCLK is an input, the SCLK is a no connect (except for the master device for which it is an output), and the FSYNC is an input. In addition, the RGDT/FSD pin operates as a delayed frame sync (FSD) and the FC/RGDT pin operates as ring detect (RGDT). In this mode, FC operation is not supported. For further details on operating the Si3021 as a slave device, refer to "Multiple Device Support" on page 25.
Clock Generation Subsystem
The Si3035 contains an on-chip clock generator. Using a single MCLK input frequency, the Si3035 can generate all the desired standard modem sample rates, as well as the common 11.025 kHz rate for audio playback. The clock generator consists of two PLLs (PLL1 and PLL2) that achieve the desired sample frequencies. Figure 23 on page 22 illustrates the clock generator.
(CF2)
P rim ary
FSYNC
P rim ary
S econdary
FC
0
D 15 - D 1 D 0 = 1 (Software F C Bit) Secondary D ata
D 15 - D 1
D 0 = 0 (Software F C Bit)
SDI
XMT D ata
XMT D ata
SDO
R CV D ata
Secondary D ata
R CV D ata
16 S C LK S
128 S C LK S
256 S C LK S
Figure 19. Software FC Secondary Request
20 Rev. 1.2
Si3035
Com m unications Fram e 1 (CF1) (CF2)
FSYNC
Prim ary
Secondary
Prim ary
FC
0
D15-D0
SDI
XMT Data
Secondary Data
XMT Data
SDO
RCV Data
Secondary Data
RCV Data
16 SCLKS 128 SCLKS
256 SCLKS
Figure 20. Hardware FC Secondary Request
FSYNC
(m ode 0)
FSYNC
(m ode 1)
D15 D14
D13 1
D12 D11 D10 D9 A A A A
D8 A
D7
D0
SDI
0
0
R/W
D7 D6 D D5 D D4 D D3 D D2 D D1 D D0 D
SDO
D
Figure 21. Secondary Communication Data Format--Read Cycle
Rev. 1.2
21
S i3 03 5
FSYNC
(m ode 0)
FSYNC
(m ode 1)
D15 D14 D13
D 12 D11 D10 A A A
D9 A
D8 A
D7 D
D6 D
D5 D
D4 D
D3 D
D2 D
D1 D0 D D
SDI
0
0
0
R/W
SDO
Figure 22. Secondary Communication Data Format--Write Cycle
FUP1
FPLL1
DIV 25
FUP2 1 0
FPLL2
MCLK
DIV N1 8 bits
PLL1
DIV M1 8 bits
DIV N2 4 bits
PLL2
DIV M2 4 bits
DIV 5
1024*Fs
0 1
DIV 16
CGM Bit
Figure 23. Clock Generation Subsystem
The architecture of the dual PLL scheme allows for fast lock time on initial start-up, fast lock time when changing modem sample rates, high noise immunity, and the ability to change modem sample rates with a single register write. A large number of MCLK frequencies between 1 MHz and 60 MHz are supported. MCLK should be from a clean source, preferably directly from a crystal with a constant frequency and no dropped pulses. In serial mode 2, the Si3021 operates as a slave device. The clock generator is configured (by default) to set the SCLK output equal to the MCLK input. The net effect is the clock generator multiplies the MCLK input by 20. For further details of slave mode operation, refer to "Multiple Device Support" on page 25. Programming the Clock Generator As noted in Figure 23, the clock generator must output a clock equal to 1024 Fs, where Fs is the desired sample rate. The 1024 Fs clock is determined through programming of the following registers:
" "
Register 7--N1 divider, 8 bits. Register 8--M1 divider, 8 bits. Register 9--N2/M2 dividers, 4 bits/4 bits. Register 10--CGM, 1 bit.
When using the Si3035 for modem applications, the clock generator can be programmed to allow for a single register write to change the modem sampling rate. These standard sample rates are shown in Table 17. The programming method is described below.
22
Rev. 1.2
Si3035
Table 17. N2, M2 Values (CGM = 0, 1)
Fs (Hz) 7200 8000 8229 8400 9000 9600 10286 N2 2 9 7 6 4 3 7 M2 2 10 8 7 5 4 10
Table 18. MCLK Examples
MCLK (MHz) 1.8432 4.0000 4.0960 5.0688 6.0000 6.1440 8.1920 9.2160 10.0000 10.3680 11.0592 12.288 14.7456 16.0000 18.4320 24.5760 25.8048 33.8688 44.2368 46.0800 47.9232 48.0000 56.0000 60.0000 PLL Lock Times The Si3035 changes sample rates very quickly. However, lock time will vary based on the programming of the clock generator. The major factor contributing to PLL lock time is the CGM bit. When the CGM bit is used (set to 1), PLL2 will lock slower than when CGM is 0. The following relationships describe the boundaries on PLL locking time:
PLL1 lock time < 1 ms (CGM = 0,1) PLL2 lock time: 100 us to 1 ms (CGM = 0) PLL2 lock time <1 ms (CGM = 1)
N1 1 5 1 11 5 1 32 1 25 9 3 1 2 5 1 32 7 147 96 5 13 125 35 25
M1 20 72 9 80 48 6 225 4 144 32 10 3 5 18 2 75 10 160 125 4 10 96 36 24
CGM 0 1 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 1
The main design consideration is the generation of a base frequency, defined as the following:
F M1 MCLK FBase = ---------------------------------- = 36.864MHz, CGM = 0 N1 M1 16 F MCLK FBase = --------------------------------------------- = 36.864MHz, CGM = 1 N1 25
N1 (Register 7) and M1 (Register 8) are 8-bit unsigned values. FMCLK is the clock provided to the MCLK pin. Table 18 lists several standard crystal oscillator rates that could be supplied to MCLK. This list simply represents a sample of MCLK frequency choices. Many more are possible. After the first PLL has been setup, the second PLL can be programmed easily. The values for N2 and M2 (Register 9) are shown in Table 17. N2 and M2 are 4-bit unsigned values. When programming the registers of the clock generator, the order of register writes is important. For PLL1 updates, N1 (Register 7) must always be written first, immediately followed by a write to M1 (Register 8). For PLL2, the CGM bit must be set as desired prior to writing N2/M2 (Register 9). Changes to the CGM bit only take effect when N2/M2 are written.
Note: The values shown in Table 17 and Table 18 satisfy the equations above. However, when programming the registers for N1, M1, N2, and M2, the value placed in these registers must be one less than the value calculated from the equations. For example, for CGM = 0 with a MCLK of 48.0 MHz, the values placed in the N1 and M1 registers would be 0x7C and 0x5F, respectively. If CGM = 1, a non-zero value must be programmed to Register 9 in order for the 16/25 ratio to take effect.
For modem designs, it is recommended that PLL1 be programmed during initialization. No further programming of PLL1 is necessary. The CGM bit and PLL2 can be programmed for the desired initial sample
Rev. 1.2 23
S i3 03 5
rate, typically 7200 Hz. All further sample rate changes are then made by simply writing to Register 9 to update PLL2. The final design consideration for the clock generator is the update rate of PLL1. The following criteria must be satisfied in order for the PLLs to remain stable:
F MCLK F = -------------------- 144 kHz UP1 N1
PDN bit is cleared. The Si3021 is fully operational, except for the ISOcap link. No communication between the Si3021 and Si3012 can occur during reset operation. Any bits associated with the Si3012 are not valid in this mode. The most common mode of operation is the normal operation. In this mode, the PDL and PDN bits are cleared. The Si3021 is fully operational and the ISOcap link is passing information between the Si3021 and the Si3012. The clock generator must be programmed to a valid sample rate prior to entering this mode. The Si3035 supports a low-power sleep mode. This mode supports the popular wake-up-on-ring feature of many modems. The clock generator registers 7, 8, and 9 must be programmed with valid non-zero values prior to enabling sleep mode. Then, the PDN bit must be set and the PDL bit cleared. When the Si3035 is in sleep mode, the MCLK signal may be stopped or remain active, but it must be active before waking up the Si3035. The Si3021 is non-functional except for the ISOcap and RGDT signal. To take the Si3035 out of sleep mode, pulse the reset pin (RESET) low. In summary, the power down/up sequence for sleep mode is as follows:
1. Registers 7, 8, and 9 must have valid non-zero values. 2. Set the PDN bit (Register 6, bit 3) and clear the PDL bit (Register 6, bit 4). 3. MCLK may stay active or stop. 4. Restore MCLK before initiating the power-up sequence. 5. Reset the Si3035 using RESET pin (after MCLK is present). 6. Program registers to desired settings.
Where FUP1 is shown in Figure 23 on page 22. Setting Generic Sample Rates The above clock generation description focuses on the common modem sample rates. An application may require a sample rate not listed in Table 17, such as the common audio rate of 11.025 kHz. The restrictions and equations above still apply; however, a more generic relationship between MCLK and Fs (the desired sample rate) is needed. The following equation describes this relationship:
5 1024 Fs M1 M2 --------------------- = ratio ------------------------------MCLK N1 N2
where Fs is the sample frequency, ratio is 1 for CGM = 0 and 25/16 for CGM = 1, and all other symbols are shown in Figure 23 on page 22. By knowing the MCLK frequency and desired sample rate, the values for the M1, N1, M2, N2 registers can be determined. When determining these values, remember to consider the range for each register as well as the minimum update rate for the first PLL. The values determined for M1, N1, M2, and N2 must be adjusted by minus one when determining the value written to the respective registers. This is due to internal logic, which adds one to the value stored in the register. This addition allows the user to write a zero value in any of the registers and the effective divide by is one. A special case occurs when both M1 and N1 and/or M2 and N2 are programmed with a zero value. When Mx and Nx are both zero, the corresponding PLLx is bypassed. Note that if M2 and N2 are set to zero, the ratio of 25/16 is eliminated and cannot be used in the above equation. In this condition the CGM bit has no effect.
The Si3035 also supports an additional power-down mode. When both the PDN (Register 6, bit 3) and PDL (Register 6, bit 4) are set, the chipset enters a complete power-down mode and draws negligible current (deep sleep mode). PLL2 should be turned off prior to entering deep sleep mode (i.e., set Register 9 to 0 and then Register 6 to 0x18). In this mode, the RGDT pin does not function. Normal operation may be restored using the same process for taking the chipset out of sleep mode.
Power Management
The Si3035 supports four basic power management operation modes: normal operation, reset operation, sleep, and full power down. The power management modes are controlled by the PDN and PDL bits of Register 6. On power up, or following a reset, the Si3035 is in reset operation. In this mode, the PDL bit is set, while the
Analog Output
The Si3035 supports an analog output (AOUT) for driving the call progress speaker found with most of today's modems. AOUT is an analog signal that is comprised of a mix of the transmit and receive signals. The receive portion of this mixed signal has a 0 dB gain, while the transmit signal has a gain of -20 dB. The AOUT level can be adjusted via the ATM and ARM bits in control Register 6. The transmit portion of the
24
Rev. 1.2
Si3035
AOUT signal can be set to -20 dB, -26 dB, -32 dB, or mute. The receive portion of the AOUT signal can be set to 0 dB, -6 dB, -12 dB, or mute. Figure 17 on page 17 illustrates a recommended application circuit. In the configuration shown, the LM386 provides a gain of 26 dB. Additional gain adjustments may be made by varying the voltage divider created by R1 and R3 of Figure 17. An LCS value of zero means the loop current is less than required for normal operation and the system should be on-hook. Typically, an LCS value of 15 means the loop current is greater than 155 mA. The LCS detector has a built-in hysteresis of 2 mA of current. This allows for a stable LCS value when the loop current is near a transition level. The LCS value is a rough approximation of the loop current, and the designer is advised to use this value in a relative means rather than an absolute value. This feature enables the host processor to detect if an additional line has "picked up" while the modem is transferring information. In the case of a second phone going off-hook, the loop current falls approximately 50% and is reflected in the value of the LCS bits.
On-Hook Line Monitor
The Si3035 allows the user to detect line activity when the device is in an on-hook state. When the system is on-hook, the line data can be passed to the DSP across the serial port while drawing a small amount of DC current from the line. This feature is similar to the passing of line information (such as caller ID), while on-hook, following a ring signal detection. To activate this feature, set the ONHM bit in Register 5. The on-hook line monitor can also be used to detect whether a phone line is physically connected to the Si3012 and associated circuitry. When the on-hook line monitor is activated (if no line is connected), the output of SDO will move towards a negative full scale value (-32768). The value is guaranteed to be at least 89% of negative full scale. If a line is present while in on-hook line monitor mode, SDO will have a near zero value. The designer must allow for the group delay of the receive filter (12/Fs) before making a decision.
Multiple Device Support
The Si3035 supports the operation of up to seven additional devices on a single serial interface. Figure 25 on page 27 shows the typical connection of the Si3035 and one additional serial voice codec (Si3000). The Si3035 must be the master in this configuration. The secondary codec should be configured as a slave device with SCLK and FSYNC as inputs. On power up, the Si3035 master will be unaware of the additional codec on the serial bus. The FC/RGDT pin is an input, operating as the hardware control for secondary frames. The RGDT/FSD pin is an output, operating as the active low ring detection signal. It is recommended that the master device be programmed for master/slave mode prior to enabling the ISOcap, because a ring signal would cause a false transition to the slave device's FSYNC. Register 14 provides the necessary control bits to configure the Si3035 for master/slave operation. Bit 0 (DCE) sets the Si3035 in master/slave mode, also referred to as daisy-chain mode. When the DCE bit is set, the FC/RGDT pin becomes the ring detect output and the RGDT/FSD pin becomes the frame sync delay output. Bits 7:5 (NSLV2:NSLV0) set the number of slaves to be supported on the serial bus. For each slave, the Si3035 will generate a FSYNC to the DSP. In daisy-chain mode, the polarity of the ring signal can be controlled by bit 1 (RPOL). When RPOL = 1, the ring detect signal (now output on the FC/RGDT pin) is active high. The Si3035 supports a variety of codecs (e.g., Si3000) as well as additional Si3035s. The type of slave codec(s) used is set by bits 4:3 (SSEL1:SSEL0). These bits determine the type of signalling used in the LSB of SDO. This assists the DSP in isolating which data stream is the master and which is the slave. If the LSB is used for
Loop Current Monitor
When the system is in an off-hook state, the LCS bits of Register 12 indicate the approximate amount of DC loop current that is flowing in the loop. The LCS is a 4-bit value ranging from zero to fifteen. Each unit represents approximately 6 mA of loop current from LCS codes 1-14. The typical LCS transfer function is shown in Figure 24.
15
10 LCS BIT 5
0 0 6 12 18 24 30 36 42 48 54 60 66 72 78 84 90 96 Loop Current (mA) 155
Figure 24. Typical LCS Transfer Function
Rev. 1.2
25
S i3 03 5
signalling, the master device will have a unique setting relative to the slave devices. The DSP can use this information to determine which FSYNC marks the beginning of a sequence of data transfers. The delayed frame sync (FSD) of each device is supplied as the FSYNC of each subsequent slave device in the daisy chain. The master Si3035 will generate an FSYNC signal for each device every 16 or 32 SCLK periods. The delay period is set by Register 14, bit 2 (FSD). Figures 26-29 show the relative timing for daisy chaining operation. Primary communication frames occur in sequence, followed by secondary communication frames, if requested. When writing/reading the master device via a secondary frame, all secondary frames of the slave devices must be written as well. When writing/reading a slave device via a secondary frame, the secondary frames of the master and all other slaves must be written as well. "No operation" writes/reads to secondary frames are accomplished by writing/reading a zero value to address zero. If FSD is set for 16 SCLK periods between FSYNCs, only serial mode 1 can be used. In addition, the slave devices must delay the tri-state to active transition of their SDO sufficiently from the rising edge of SCLK to avoid bus contention. The Si3035 supports the operation of up to eight Si3035 devices on a single serial bus. The master Si3035 must be configured in serial mode 1. The slave(s) Si3035 is configured in serial mode 2. Figure 30 shows a typical master/slave connection using three Si3035 devices. When in serial mode 2, FSYNC becomes an input, RGDT/FSD becomes the delay frame sync output, and FC/RGDT becomes the ring detection output. In addition, the internal PLLs are fixed to a multiply by 20. This provides the desired sample rate when the master's SCLK is provided to the slave's MCLK. The SCLK of the slave is a no connect in this configuration. The delay between FSYNC input and delayed frame sync output (RGDT/FSD) will be 16 SCLK periods. The RGDT/FSD output has a waveform identical to the FSYNC signal in serial mode 0. In addition, the LSB of SDO is set to zero by default for all devices in serial mode 2.
Register 13 must be 0. The receive path can support gains of 0, 3, 6, 9, and 12 dB. The gain is selected by bits 2:0 (ARX2:ARX0). The receive path can also be muted by setting bit 3 (RXM). The transmit path can support attenuations of 0, 3, 6, 9, and 12 dB. The attenuation is selected by bits 6:4 (ATX2:ATX0). The transmit path can also be muted by setting bit 7 (TXM).
Filter Selection
The Si3035 supports additional filter selections for the receive and transmit signals. When set, the IIRE bit of Register 16 enables the IIR filters defined in Table 12 on page 11. This filter provides a much lower, however non-linear, group delay than the default FIR filters.
Gain Control
The Si3035 supports multiple gain and attenuation settings for the receive and transmit paths, respectively, via Register 13. When the ARX bit is set, 6 dB of gain is applied to the receive path. When the ATX bit is set, -3 dB of gain is applied to the transmit path. Register 15 can be used to provide additional gain control. For Register 15 to have an effect on the receive and transmit paths, the ATX and ARX bits of
26 Rev. 1.2
Si3035
MCLK DSP SCLK SDO SDI FSYNC Si3021 MCLK SCLK SDI SDO FSYNC
INT0
FC/RGDT RGDT/FSD M0 M1
VCC
47 k
47 k
+5 V 47 k
Si3000 SCLK MCLK FSYNC SDI SDO Voice Codec
Figure 25. Typical Connection for Master/Slave Operation (e.g., Data/Fax/Voice Modem)
Rev. 1.2
27
S i3 03 5
Master Slave 1 Serial Mode 1 Reg 14: NSLV = 1 , SSEL = 2, FSD = 0, DCE = 1 Serial Mode 2 Reg 14 Reset valu es: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
P rim a ry F ra m e (D a ta ) S e c o n d a ry F ra m e (C o n tro l)
128 SCLKs
128 SCLKs
Master FSYNC
32 SCLKs Master FSD/ Slave1 FSYNC
32 SCLKs
SDI [0] SDI [15..1] SDO [0] SDO [15..1]
1 Master 1 Master
1 Slave1 0 Slave1
Master Master Master Master
Slave1 Slave1 Slave1 Slave1
Comments
Primary frames with secondary frame requested via S DI[0] = 1
Figure 26. Daisy Chaining of a Single Slave (Pulse FSD)
Master Slave 1
Serial Mode 1 Reg 14: NSLV = 1 , SSEL = 2, FSD = 1, DCE = 1 Serial Mode 2 Reg 14 Reset valu es: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
P rim a ry F ra m e (D a ta ) S e c o n d a ry F ra m e (C o n tro l)
128 SCLKs
128 SCLKs
Master FSYNC
Master FSD/ Slave1 FSYNC
16 SCLKs
16 SCLKs
16 SCLKs
16 SCLKs
SDI [0] SDI [15..1] SDO [0] SDO [15..1]
1 Master 1 Master
1 Slave1 0 Slave1
Master Master Master Master
Slave1 Slave1 Slave1 Slave1
Comments
Primary frames with secondary frame requested via S DI[0] = 1
Figure 27. Daisy Chaining of a Single Slave (Frame FSD)
28
Rev. 1.2
Master Slave 1
Serial Mode 1 Reg 14: NSLV = 7, SSEL = 2, FSD = 1, DCE = 1 Serial Mode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 Primary Frame (Data) Secondary Frame (Control)
128 SCLKs
Master FSYNC 16 SCLKs Master FSD/ Slave1 FSYNC
128 SCLKs
Slave1 FSD/ Slave2 FSYNC
Slave2 FSD/ Slave3 FSYNC
Rev. 1.2 29
Slave3 FSD/ Slave4 FSYNC
Slave4 FSD/ Slave5 FSYNC
Slave5 FSD/ Slave6 FSYNC
Slave6 FSD/ Slave7 FSYNC
SDI [0] SDI [15..1] SDO [0] SDO[15..1] Comments
1 Master 1 Master
1 Slave1 0 Slave1
1 Slave2 0 Slave2
1 Slave3 0 Slave3
1 Slave4 0 Slave4
1 Slave5 0 Slave5
1 Slave6 0 Slave6
1 Slave7 0 Slave7
Master Master Master Master
Slave1 Slave1 Slave1 Slave1
Slave2 Slave2 Slave2 Slave2
Slave3 Slave3 Slave3 Slave3
Slave4 Slave4 Slave4 Slave4
Slave5 Slave5 Slave5 Slave5
Slave6 Slave6 Slave6 Slave6
Slave7 Slave7 Slave7 Slave7
Primary frames with secondary frame requested via SDI[0] = 1
Si3035
Figure 28. Daisy Chaining of Eight DAAs
S i3 03 5
Master Slave 1 Serial Mode 0 Reg 14: NSLV = 1 , SSEL = 2, FSD = 0, DCE = 1 Serial Mode 2 Reg 14 Reset valu es: NSLV = 1, SSEL = 3, FSD = 1, D CE = 1
P rim a ry F ra m e (D a ta ) S e c o n d a ry F ra m e (C o n tro l)
128 SCLKs
128 SCLKs
16 SCLKs
Master FSYNC
Master FSD/ Slave1 FSYNC
SDI [0] SDI [15..1] SDO [0] SDO [15..1]
1 Master 1 Master
1 Slave1 0 Slave1
Master Master Master Master
Slave1 Slave1 Slave1 Slave1
Comments
Primary frames with secondary frame requested via SD I[0] = 1
Figure 29. Daisy Chaining with Framed FSYNC and Framed FSD
30
Rev. 1.2
Si3035
MCLK DSP SCLK SDO SDI FSYNC Si3021-M aster MCLK SCLK SDI SDO FSYNC
INT0 VCC
FC/RGDT RGDT/FSD M1 M0
47 k
47 k
Si3021-Slave 1 MCLK SCLK FSYNC SDI SDO RGDT/FSD VCC M1 M0
Si3021-Slave 2 MCLK SCLK FSYNC SDI SDO RGDT/FSD VCC M1 M0
Figure 30. Typical Connection for Multiple Si3035s
Rev. 1.2
31
S i3 03 5
Revision Identification
The Si3035 provides the system designer the ability to determine the revision of the Si3021 and/or the Si3012. Register 11 identifies the revision of the Si3021 with 4 bits named REVA. Register 13 identifies the revision of the Si3012 with 4 bits named REVB. Table 19 shows the values for the various revisions. can be used, the test circuit in Figure 1 on page 4 is adequate. In addition, an off-hook sequence must be performed to connect the power source to the line-side chip. For the start-up test mode, no line-side power is necessary and no off-hook sequence is required. The start-up test mode is enabled by default. When the PDL bit (Register 6, bit 4) is set (the default case), the line side is in a power-down mode and the DSP-side is in a digital loop-back mode. In this mode, data received on SDI is passed through the internal filters and transmitted on SDO. This path will introduce approximately 0.9 dB of attenuation on the SDI signal received. The group delay of both transmit and receive filters will exist between SDI and SDO. Clearing the PDL bit disables this mode and the SDO data is switched to the receive data from the line side. When the PDL bit is cleared the FDT bit (Register 12, bit 6) will become active, indicating the successful communication between the line-side and DSP-side. This can be used to verify that the ISOcap link is operational. The remaining test modes require an off-hook sequence to operate. The following sequence defines the off-hook requirement:
1. Power up or reset. 2. Program clock generator to desired sample rate. 3. Enable line-side by clearing PDL bit. 4. Issue off-hook 5. Delay 1548/Fs to allow calibration to occur. 6. Set desired test mode.
Table 19. Revision Values
Revision A B C D E G Si3021 1000 1001 1010 -- -- -- Si3012 -- -- -- 0100 0101 0111
Calibration
The Si3035 initiates an auto-calibration by default whenever the device goes off-hook or experiences a loss in line power. Calibration is used to remove any offsets that may be present in the on-chip A/D converter which could affect the A/D dynamic range. Auto-calibration is typically initiated after the DAA DC termination stabilizes and takes 512/Fs seconds to complete. Due to the large variation in line conditions and line card behavior that may be presented to the DAA, it can be beneficial to use manual calibration in lieu of auto-calibration. Manual calibration should be executed as close as possible to 512/Fs seconds before valid transmit/receive data is expected. The following steps should be taken to implement manual calibration:
1. The CALD (auto-calibration disable--Register 17) bit must be set to 1. 2. The MCAL (manual calibration) bit must be toggled to 1 and then 0 to begin and complete the calibration. 3. The calibration will be completed in 512/Fs seconds.
The ISOcap digital loopback mode allows the data pump to provide a digital input test pattern on SDI and receive that digital test pattern back on SDO. To enable this mode, set the DL bit of Register 1. In this mode, the isolation barrier is actually being tested. The digital stream is delivered across the isolation capacitor, C1 of Figure 16 on page 15, to the line-side device and returned across the same barrier. In this mode, the 0.9 dB attenuation and filter group delays also exist. The analog loopback mode allows an external device to drive the RX pin of the line-side chip and receive the signal from the TX pin. This mode allows testing of external components connecting the RJ-11 jack (TIP and RING) to the line side of the Si3035. To enable this mode, set the AL bit of Register 2. The final testing mode, internal analog loopback, allows the system to test the basic operation of the transmit/receive path of the line side and the external components R4, R18, R21, and C5 of Figure 16 on page 15. In this test mode, the data pump provides a
In-Circuit Testing
The Si3035's advanced design provides the modem manufacturer with an increased ability to determine system functionality during production line tests, as well as support for end-user diagnostics. Four loopback modes exist allowing increased coverage of system components. For three of the test modes, a line-side power source is needed. While a standard phone line
32
Rev. 1.2
Si3035
digital test waveform on SDI. This data is passed across the isolation barrier, looped from the TX to the RX pin, passed back across the isolation barrier, and presented to the data pump on SDO. To enable this mode, clear the HBE bit of Register 2. Clearing the HBE bit will cause a DC offset which affects the signal swing of the transmit signal. In this test mode, it is recommended that the transmit signal be 12 dB lower than normal transmit levels. This lower level will eliminate clipping caused by the DC offset which results from disabling the hybrid. It is assumed in this test that the line AC impedance is nominally 600 .
Note: All test modes are mutually exclusive. If more than one test mode is enabled concurrently, the results are unpredictable.
chip must be reset. This is accomplished by setting the PDL bit for at least 1 ms. Another useful bit is the communication link error (CLE) bit (Register 12, bit 7). The CLE bit indicates a time-out error for the ISOcap link following a change to either PLL1 or PLL2. For more information, see "Clock Generation Subsystem" on page 20. When the CLE bit is set, the DSP-side chip has failed to receive verification from the line side that the clock change has been accepted in an expected period of time (less than 10 ms). This condition indicates a severe error in programming the clock generator or possibly a defective line-side chip.
Exception Handling
The Si3035 provides several mechanisms to determine if an error occurs during operation. Through the secondary frames of the serial link, the controlling DSP can read several status bits. The bit of highest importance is the frame detect bit (FDT, Register 12, bit 6). This bit indicates that the DSP-side (Si3021) and line-side (Si3012) devices are communicating. During normal operation, the FDT bit can be checked before reading any bits that indicate information about the line side. If FDT is not set, the following bits related to the line-side are invalid: RDT, LCS, CBID, and REVB. The RGDT operation will also be non-functional. Following power-up and reset, the FDT bit is not set because the PDL bit (Register 6, bit 4) defaults to 1. In this state, the ISOcap link is not operating and no information about the line-side can be determined. The user must program the clock generator to a valid configuration for the system and clear the PDL bit to activate the ISOcap link. While the Si3021 and Si3012 are establishing communication, the Si3035 will not generate FSYNC signals. Establishing communication will take less than 10 ms. Therefore, if the controlling DSP serial interface is interrupt driven, based on the FSYNC signal, the controlling DSP does not require a special delay loop to wait for this event to complete. The FDT bit can also indicate if the line-side executes an off-hook request successfully. If the line-side is not connected to a phone line (i.e., the user fails to connect a phone line to the modem), the FDT bit remains cleared. The controlling DSP must allow sufficient time for the line-side to execute the off-hook request. The maximum time for FDT to be valid following an off-hook request is 10 ms. At this time, the LCS bits indicate the amount of loop current flowing. For more information, see "Loop Current Monitor" on page 25. If the FDT bit fails to be set following an off-hook request, the line-side
Rev. 1.2 33
S i3 03 5
Control Registers
Any register not listed here is reserved and should not be written.
Table 20. Register Summary
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Control 1 Control 2 Control 3 Control 4 DAA Control 1 DAA Control 2 PLL1 Divide N1 PLL1 Multiply M1 PLL2 Div./Mult. N2/M2 PLL Control Chip Revision Line Side Status Transmit and Receive Gain Daisy-Chain Control TX/RX Gain Control IIR Filter Control Calibration
SR AL
DL HBE
SB RXE
OPOL CPE ATM1 ARM1 PDL
ONHM PDN
RDT
OHE ATM0
OH ARM0
N1[7:0] M1[7:0] N2[3:0] M2[3:0] CGM REVA[3:0] CLE FDT CBID NSLV2 TXM 0 0 NSLV1 ATX2 0 MCAL NSLV0 ATX1 0 CALD REVB[3:0] SSEL1 ATX0 IIRE SSEL0 RXM 1 FSD ARX2 0 LCS[3:0] ARX RPOL ARX1 0 ATX DCE ARX0 0
34
Rev. 1.2
Si3035
Register 1. Control 1 Bit Name Type D7 SR R/W D6 D5 D4 D3 D2 D1 DL R/W D0 SB R/W
Reset settings = 0000_0000 Bit 7 Name SR Software Reset. 0 = Enables chip for normal operation. 1 = Sets all registers to their reset value. Read returns zero. Isolation Digital Loopback. 0 = Disables digital loopback mode across the isolation barrier. 1 = Enables digital loopback mode across the isolation barrier. Serial Digital Interface Mode. 0 = Operation is in 15-bit mode and the LSB of the data field indicates whether a secondary frame is required. 1 = The serial port is operating in 16-bit mode and requires use of the secondary frame sync signal, FC/RGDT, to initiate control data reads/writes. Function
6:2 1
Reserved DL
0
SB
Register 2. Control 2 Bit Name Type Reset settings = 0000_0011 Bit 7:4 3 Name Reserved AL Read returns zero. Analog Loopback. 0 = Disables analog loopback mode. 1 = Enables analog loopback mode. Read returns zero. Hybrid Enable. 0 = Disconnects hybrid in transmit path. 1 = Connects hybrid in transmit path. Receive Enable. 0 = Disables receive path. 1 = Enables receive path. Function D7 D6 D5 D4 D3 AL R/W D2 D1 HBE R/W D0 RXE R/W
2 1
Reserved HBE
0
RXE
Rev. 1.2
35
S i3 03 5
Register 3. Control 3 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name Reserved Read returns zero. Function D7 D6 D5 D4 D3 D2 D1 D0
Register 4. Control 4 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name Reserved Read returns zero. Function D7 D6 D5 D4 D3 D2 D1 D0
36
Rev. 1.2
Si3035
Register 5. DAA Control 1 Bit Name Type Reset settings = 0000_0000 Bit 7:5 4 Name Reserved OPOL Read returns zero. Off-Hook Polarity. 0 = Off-hook pin is active low. 1 = Off-hook pin is active high. On-Hook Line Monitor. 0 = Normal on-hook mode. 1 = Enables low-power monitoring mode allowing the DSP to receive line activity without going off-hook. This mode is used for caller ID detection. Ring Detect. 0 = No ring is occurring. Reset either 4.5-9 seconds after last positive ring is detected or when the system executes an off-hook. 1 = Indicates a ring is occurring. Off-Hook Pin Enable. 0 = Off-hook pin is ignored. 1 = Enables the operation of the off-hook pin. Off-Hook. 0 = Line side chip is on-hook. 1 = Causes the line side chip to go off-hook. This bit operates independently of OHE and is a logic OR with the off-hook pin when OHE = 1. Function D7 D6 D5 D4 OPOL R/W D3 ONHM R/W D2 RDT R D1 OHE R/W D0 OH R/W
3
ONHM
2
RDT
1
OHE
0
OH
Rev. 1.2
37
S i3 03 5
Register 6. DAA Control 2 Bit Name Type D7 CPE R/W D6 D5 D4 PDL R/W D3 PDN R/W D2 D1 D0
ATM1 ARM1 R/W R/W
ATM0 ARM0 R/W R/W
Reset settings = 0111_0000 Bit 7 Name CPE Function Charge Pump Enable. 0 = Charge pump is disabled. 1 = Charge pump is enabled. (The VA pin should not be connected to a supply. VD = 3.3 V 10%.) AOUT Transmit Path Level Control. 00 = -20 dB transmit path attenuation for call progress AOUT pin only. 01 = -32 dB transmit path attenuation for call progress AOUT pin only. 10 = Mutes transmit path for call progress AOUT pin only. 11 = -26 dB transmit path attenuation for call progress AOUT pin only.
6,1
ATM[1:0]
5,0
ARM[1:0] AOUT Receive Path Level Control. 00 = 0 dB receive path attenuation for call progress AOUT pin only. 01 = -12 dB receive path attenuation for call progress AOUT pin only. 10 = Mutes receive path for call progress AOUT pin only. 11 = -6 dB receive path attenuation for call progress AOUT pin only. PDL Power Down Line-Side Chip. 0 = Normal operation. Program the clock generator before clearing this bit. 1 = Places the Si3012 in power down or reset state. Power Down. 0 = Normal operation. 1 = Powers down the Si3021. A pulse on RESET is required to restore normal operation.
4
3
PDN
2
Reserved Read returns zero.
Register 7. PLL1 Divide N1 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
N1[7:0] R/W
Reset settings = 0000_0000 (serial mode 0, 1, 2) Bit 7:0 Name N1[7:0] Function N1 Divider. Contains the (value - 1) for determining the output frequency on PLL1.
38
Rev. 1.2
Si3035
Register 8. PLL1 Multiply M1 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
M1[7:0] R/W
Reset settings = 0000_0000 (serial mode 0, 1) Reset settings = 0001_0011 (serial mode 2) Bit 7:0 Name M1[7:0] Function M1 Multiplier. Contains the (value - 1) for determining the output frequency on PLL1
Register 9. PLL2 Divide/Multiply N2/M2 Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0
N2[3:0] R/W
M2[3:0] R/W
Reset settings = 0000_0000 (serial mode 0, 1, 2) Bit 7:4 3:0 Name N2[3:0] M2[3:0] Function N2 Divider. Contains the (value - 1) for determining the output frequency on PLL2. M2 Multiplier. Contains the (value - 1) for determining the output frequency on PLL2.
Register 10. PLL Control Register Bit Name Type Reset settings = 0000_0000 Bit 7:1 0 Name Reserved CGM Read returns zero. Clock Generation Mode. 0 = No additional ratio is applied to the PLL and faster lock times are possible. 1 = A 25/16 ratio is applied to the PLL allowing for a more flexible choice of MCLK frequencies while slowing down the PLL lock time. Function D7 D6 D5 D4 D3 D2 D1 D0 CGM R/W
Rev. 1.2
39
S i3 03 5
Register 11. Chip Revision Bit Name Type Reset settings = N/A Bit 7:4 3:0 Name Reserved REVA[3:0] Read returns zero. Chip Revision. Four-bit value indicating the revision of the Si3021 (DSP-side) chip. Function D7 D6 D5 D4 D3 D2 D1 D0
REVA R[3:0]
Register 12. Line Side Status Bit Name Type D7 CLE R/W D6 FDT R D5 D4 D3 D2 D1 D0
LCS[3:0] R
Reset settings = N/A Bit 7 Name CLE Function Communications (ISOcap Link) Error. 0 = ISOcap communication link between the Si3021 and the Si3012 is operating correctly. 1 = Indicates a communication problem between the Si3021 and the Si3012. A write of 0 or a reset is required to clear this bit. Frame Detect. 0 = Indicates ISOcap link has not established frame lock. 1 = Indicates ISOcap link frame lock has been established. Read returns zero. Loop Current Sense. Four-bit value returning the loop current in 6 mA increments. 0 = Loop current < 0.4 mA typical. 1111 = Loop current > 155 mA typical. See "Loop Current Monitor" on page 25.
6
FDT
5:4 3:0
Reserved LCS[3:0]
40
Rev. 1.2
Si3035
Register 13. Transmit and Receive Gain Bit Name Type D7 D6 CBID R D5 D4 D3 D2 D1 ARX R/W D0 ATX R/W
REVB[3:0] R
Reset settings = 0000_0000 Bit 7 6 Name Reserved CBID Read returns zero. Chip B ID. 0 = Indicates the line side is domestic only. 1 = Indicates the line side has international support. Function
5:2 1
REVB[3:0] Chip Revision. Four-bit value indicating the revision of the Si3012 (line-side) chip. ARX Receive Gain. 0 = 0 dB gain is applied to the receive path. 1 = 6 dB gain is applied to the receive path.
Note: This bit should be zero if using Register 15 to control gain.
0
ATX
Transmit Gain. 0 = 0 dB gain is applied to the receive path. 1 = -3 dB gain (attenuation) is applied to the transmit path.
Note: This bit should be 0 if using Register 15 to control gain.
Rev. 1.2
41
S i3 03 5
Register 14. Daisy-Chain Control Bit Name Type D7 D6 D5 D4 D3 D2 FSD R/W D1 D0
NSLV2 NSLV1 NSLV0 SSEL1 SSEL0 R/W R/W R/W R/W R/W
RPOL DCE R/W R/W
Reset settings = 0000_0010 (serial mode 0, 1) Reset settings = 0011_1111 (serial mode 2) Bit 7:5 Name Function
NSLV[2:0] Number of Slave Devices. 000 = 0 slaves. Simply redefines the FC/RGDT and RGDT/FSD pins. 001 = 1 slave device. 010 = 2 slave devices. 011 = 3 slave devices. 100 = 4 slave devices. (For four or more slave devices, the FSD bit MUST be set.) 101 = 5 slave devices. 110 = 6 slave devices. 111 = 7 slave devices. SSEL[1:0] Slave Device Select. 00 = 16-bit SDO receive data. 01 = Reserved. 10 = 15-bit SDO receive data. LSB = 1 for the Si3035 device. 11 = 15-bit SDO receive data. LSB = 0 for the Si3035 device. FSD Delayed Frame Sync Control. 0 = Sets the number of SCLK periods between frame syncs to 32. 1 = Sets the number of SCLK periods between frame syncs to 16. This bit MUST be set when Si3035 devices are slaves. For the master Si3035, only serial mode 1 is allowed in this case. Ring Detect Polarity. 0 = The FC/RGDT pin (operating as ring detect) is active low. 1 = The FC/RGDT pin (operating as ring detect) is active high. Daisy-Chain Enable. 0 = Daisy chaining disabled. 1 = Enables the Si3035 to operate with slave devices on the same serial bus. The FC/RGDT signal (pin 7) becomes the ring detect output and the RDGT/FSD signal (pin 15) becomes the delayed frame sync signal. Note that ALL other bits in this register are ignored if DCE = 0.
4:3
2
1
RPOL
0
DCE
42
Rev. 1.2
Si3035
Register 15.TX/RX Gain Control Bit Name Type D7 TXM R/W D6 ATX2 R/W D5 ATX1 R/W D4 ATX0 R/W D3 RXM R/W D2 ARX2 R/W D1 ARX1 R/W D0 ARX0 R/W
Reset settings = 0000_0000 Bit 7 Name TXM Transmit Mute. 0 = Transmit signal is not muted. 1 = Mutes the transmit signal. Analog Transmit Attenuation. 000 = 0 dB attenuation. 001 = 3 dB attenuation. 010 = 6 dB attenuation. 011 = 9 dB attenuation. 1xx = 12 dB attenuation.
Note: Register 13 ATX bit must be 0 if these bits are used.
Function
6:4
ATX[2:0]
3
RXM
Receive Mute. 0 = Receive signal is not muted. 1 = Mutes the receive signal. Analog Receive Gain. 000 = 0 dB gain. 001 = 3 dB gain. 010 = 6 dB gain. 011 = 9 dB gain 1xx = 12 dB gain.
Note: Register 13 ARX bit must be 0 if these bits are used.
2:0
ARX[2:0]
Rev. 1.2
43
S i3 03 5
Register 16. IIR Filter Control Bit Name Type D7 0 R/W D6 0 R/W D5 0 R/W D4 IIRE R/W D3 1 R/W D2 0 R/W D1 0 R/W D0 0 R/W
Reset settings = 0000_1000 Bit 7:5 4 Name Reserved IIRE Function Read returns zero (must always be written with zeroes). IIR Filter Enable. 0 = FIR filter enabled. 1 = Transmit and receive filters are realized with an IIR filter characteristic. To enable IIR filter write 0x18; to disable IIR filter write 0x08. See Table 12 on page 11 for more details on IIR filter performance. Read returns 0x8 (must always be written with 0x8).
3:0
Reserved
Register 17. International Control Bit Name Type D7 0 D6 MCAL R/W D5 CALD R/W D4 D3 D2 D1 D0
Reset settings = 0000_0000 Bit 7 6 Name Reserved MCAL Must be zero. Manual Calibration. 0 = No calibration. 1 = Initiate calibration. Auto-Calibration. 0 = Auto-calibration enabled. 1 = Auto-calibration disabled. Read returns zero. Function
5
CALD
4:0
Reserved
44
Rev. 1.2
Si3035 AP P E N D I X --U L1 950 3 R D EDI T I O N
Although designs using the Si3035 comply with UL1950 3rd Edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 31 shows two designs that can pass the UL1950 overvoltage tests, as well as electromagnetic emissions. The top schematic of Figure 31 shows the configuration in which the ferrite beads (FB1, FB2) are on the unprotected side of the sidactor (RV1). For this configuration, the current rating of the ferrite beads needs to be 6 A. However, the higher current ferrite beads are less effective in reducing electromagnetic emissions. The bottom schematic of Figure 31 shows the configuration in which the ferrite beads (FB1, FB2) are on the protected side of the sidactor (RV1). For this design, the ferrite beads can be rated at 200 mA. In a cost optimized design, it is important to remember that compliance to UL1950 does not always require overvoltage tests. It is best to plan ahead and know which overvoltage tests will apply to your system. System-level elements in the construction, such as fire enclosure and spacing requirements, need to be considered during the design stages. Consult with your professional testing agency during the design of the product to determine which tests apply to your system.
C24 75 @ 100 MHz, 6 A 1.25 A FB1 TIP
RV1
75 @ 100 MHz, 6 A FB2 RING
C25
C24 600 @ 100 MHz, 200 m A FB1 1.25 A TIP
RV1 FB2 RING 600 @ 100 MHz, 200 m A
C25
Figure 31. Circuits that Pass all UL1950 Overvoltage Tests
Rev. 1.2 45
S i3 03 5
Pin Descriptions: Si3021
Si3021 (SOIC)
MCLK FSYNC SCLK VD SDO SDI FC/RGDT RESET 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OFHK RGDT/FSD M0 VA GND C1A M1 AOUT SDO SDI FC/RGDT RESET AOUT M1 C1A GND
Si3021 (TSSOP)
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VD SCLK FSYNC MCLK OFHK RGDT/FSD M0 VA
Table 21. Si3021 Pin Descriptions
SOIC Pin # 1 TSSOP Pin # 13 Pin Name MCLK Description Master Clock Input. High speed master clock input. Generally supplied by the system crystal clock or modem/DSP. Frame Sync Output. Data framing signal that is used to indicate the start and stop of a communication/data frame. Serial Port Bit Clock Output. Controls the serial data on SDO and latches the data on SDI. Digital Supply Voltage. Provides the digital supply voltage to the Si3021, nominally either 5 V or 3.3 V. Serial Port Data Output. Serial communication data that is provided by the Si3021 to the modem/DSP. Serial Port Data Input. Serial communication and control data that is generated by the modem/DSP and presented as an input to the Si3021. Secondary Transfer Request Input/Ring Detect Output. An optional signal to instruct the Si3021 that control data is being requested in a secondary frame. When daisy chain is enabled, this pin becomes the ring detect output. Produces an active low rectified version of the ring signal. Reset Input. An active low input that is used to reset all control registers to a defined, initialized state. Also used to bring the Si3034 out of sleep mode. Analog Speaker Output. Provides an analog output signal for driving a call progress speaker.
2
14
FSYNC
3
15
SCLK
4
16
VD
5
1
SDO
6
2
SDI
7
3
FC/RGDT
8
4
RESET
9
5
AOUT
46
Rev. 1.2
Si3035
Table 21. Si3021 Pin Descriptions (Continued)
SOIC Pin # 10 TSSOP Pin # 6 Pin Name M1 Description Mode Select 1 Input. The second of two mode select pins that is used to select the operation of the serial port/DSP interface. Isolation Capacitor 1A. Connects to one side of the isolation capacitor C1. Used to communicated with the line-side device. Ground. Connects to the system digital ground. Analog Supply Voltage. Provides the analog supply voltage for the Si3021, nominally 5 V. This supply is typically generated internally with an on-chip charge pump set through a control register. Mode Select 0 Input. The first of two mode select pins that is used to select the operation of the serial port/DSP interface. Ring Detect/Delayed Frame Sync Output. Output signal that indicates the status of a ring signal. Produces an active low rectified version of the ring signal. When daisy chain is enabled, this signal becomes a delayed frame sync to drive a slave device. Off-Hook Input. An active low input control signal that provides a termination across TIP and RING for line seizing and pulse dialing.
11
7
C1A
12
8
GND
13
9
VA
14
10
M0
15
11
RGDT/FSD
16
12
OFHK
Rev. 1.2
47
S i3 03 5
Pin Descriptions: Si3012
Si3012 (SOIC or TSSOP)
TSTA TSTB IGND C1B RNG1 RNG2 QB QE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 TX NC RX REXT DCT HYBD VREG2 VREG
Table 22. Si3012 Pin Descriptions
(SOIC or TSSOP) Pin # 1 Pin Name TSTA Description Test Input A. Allows access to test modes which are reserved for factory use. This pin has an internal pull-up and should be left as a no connect for normal operation. Test Input B. Allows access to test modes which are reserved for factory use. This pin has an internal pull-up and should be left as a no connect for normal operation. Isolated Ground. Connects to ground on the line-side interface. Isolation Capacitor 1B. Connects to one side of isolation capacitor C1. Ring 1 Input. Connects through a capacitor to the TIP lead of the telephone line. Provides the ring and caller ID signals to the Si3035. Ring 2 Input. Connects through a capacitor to the RING lead of the telephone line. Provides the ring and caller ID signals to the Si3035. Transistor Base. Connects to the base of the hookswitch transistor, Q3. Transistor Emitter. Connects to the emitter of the hookswitch transistor, Q3. Voltage Regulator. Connects to an external capacitor to provide bypassing for an internal voltage regulator. Voltage Regulator 2. Connects to an external capacitor to provide bypassing for an internal voltage regulator.
2
TSTB
3 4 5
IGND C1B RNG1
6
RNG2
7 8 9
QB QE VREG
10
VREG2
48
Rev. 1.2
Si3035
Table 22. Si3012 Pin Descriptions (Continued)
(SOIC or TSSOP) Pin # 11 12 13 14 15 16 Pin Name HYBD DCT REXT RX NC TX Description Hybrid Node Output. Balancing capacitor connection used for JATE out-of-band noise support. DC Termination. Provides DC termination to the telephone network. External Resistor. Connects to an external resistor. Receive Input. Serves as the receive-side input from the telephone network. No Connect. Transmit Output. Provides the output through an AC termination impedance to the telephone network.
Rev. 1.2
49
S i3 03 5
Ordering Guide
Table 23. Ordering Guide
Chipset Si3034 Si3035 Si3036 Si3038 Si3044 Si3044 Si3046 Si3048 Region Global FCC/Japan FCC/Japan Global Enhanced Global Enhanced Global FCC/JATE Global Interface DSP Serial I/F DSP Serial I/F AC Link AC Link DSP Serial I/F DSP Serial I/F AC Link AC Link Digital (SOIC) SI3021-KS SI3021-KS Si3024-KS Si3024-KS SI3021-KS Si3021-BS Si3025-KS Si3025-KS Line (SOIC) Si3014-KS Si3012-KS Si3012-KS Si3014-KS Si3015-KS Si3015-BS Si3012-KS Si3014-KS Digital (TSSOP) Si3021-KT Si3021-KT Si3024-KT Si3024-KT Line (TSSOP) Si3014-KT Si3012-KT Si3012-KT Si3014-KT Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to 85C 0C to 70C 0C to 70C
50
Rev. 1.2
Si3035
SOIC Outline
Figure 32 illustrates the package details for the Si3021 and Si3012. Table 24 lists the values for the dimensions shown in the illustration.
Figure 32. 16-pin Small Outline Plastic Package (SOIC)
Table 24. Package Diagram Dimensions
Controlling Dimension: mm Symbol Min A A1 A2 b c D E e H L L1 0.053 0.004 0.051 0.013 0.007 0.386 0.150 0.050 BSC 0.228 0.016 0.042 BSC -- 0 Inches Max 0.069 0.010 0.059 0.020 0.010 0.394 0.157 -- 0.244 0.050 -- 0.004 8 Millimeters Min 1.35 0.10 1.30 0.330 0.19 9.80 3.80 1.27 BSC 5.80 0.40 1.07 BSC -- 0 Max 1.75 0.25 1.50 0.51 0.25 10.01 4.00 -- 6.20 1.27 -- 0.10 8
Rev. 1.2
51
S i3 03 5
TSSOP Outline
Figure 33 illustrates the package details for the Si3021 and Si3014. Table 25 lists the values for the dimensions shown in the illustration.
E1
E
2
R1 R
1
S
L L1
e
3
D
A2
A
c
b A1
Figure 33. 16-pin Thin Small Shrink Outline Package (TSSOP)
Table 25. Package Diagram Dimensions
Symbol A A1 A2 b c D e E E1 L L1 R R1 S 1 2 3 Min -- 0.05 0.80 0.19 0.09 4.85 Millimeters Nom 1.10 -- 1.00 -- -- 5.00 0.65 BSC 6.40 BSC 4.40 0.60 1.00 REF -- -- -- -- 12 REF 12 REF Max 1.20 0.15 1.05 0.30 0.20 5.15
4.30 0.45 0.09 0.09 0.20 0
4.50 0.75 -- -- -- 8
52
Rev. 1.2
Si3035
Data Sheet Changes from Version 1.0 to Version 1.1
! !
! !
Typical Application Circuit was updated. C24, C25 value changed from 470 pF to 1000 pF and C31, C32 were added in Table 13. The tolerance was also changed from 20% to 10%. Power Supply Voltage, Analog maximum changed from 4.75 V to 5.00 V in Table 4. Last paragraph updated in "Power Management" text section.
Data Sheet Changes from Version 1.1 to Version 1.2
! ! ! ! ! ! ! !
TSSOP information added. Total supply currents updated in Table 3 and Table 4. Cycle time updated in Table 7. Delay times updated in Table 8, Table 9, and Table 10. Figure 4 updated. Revision G values added in Table 19. Figure 16, "Typical Application Schematic," on page 15 updated. Table 13, "Component Values--Typical Application," on page 16 (BOM) updated.
Rev. 1.2
53
S i3 03 5
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ISOcap are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
54
Rev. 1.2

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